Method of chemical-mechanical polishing

ABSTRACT

A method of polishing a metal layer comprising the following steps. A structure having an upper patterned dielectric layer with an opening therein is provided. A barrier layer is formed over the patterned upper dielectric layer and lining the opening. A metal layer is formed over the barrier layer, filling the opening. A first polish step employing a first slurry composition is conducted to remove a portion of the overlying metal layer. A second polish step employing the first slurry composition is conducted to: polish the partially removed overlying metal layer; and to expose portions of the barrier layer overlying the patterned upper dielectric layer. A third polish step employing a second slurry composition is conducted to remove the exposed barrier layer portions and exposing underlying portions of the patterned upper dielectric layer. A fourth polish step employing the second slurry composition and BTA is conducted to buff the exposed upper dielectric layer portions.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation of co-pending U.S. nonprovisional patent application Ser. No. 10/627,795, filed Jul. 25, 2003, to Chen et al., titled “Barrier-Slurry-Free Copper CMP Process,” which is related to co-pending application Ser. No. 10/714,985, filed Nov. 17, 2003, titled “Copper CMP Defect Reduction by Extra Slurry Polish;” the entirety of which applications are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor fabrication and more specifically to polishing semiconductor metal layers.

BACKGROUND OF THE INVENTION

During metal/copper chemical mechanical polishing processes, three films/materials are encountered. 1) A patterned dielectric layer, usually silicon oxide (oxide), within which an opening is formed; 2) a barrier layer which lines the oxide layer opening and covers the top of the patterned oxide layer; and 3) a metal layer, usually copper, formed over the patterned dielectric layer, filling the barrier lined opening. In order to planarize, or polish, the metal layer to form a planarized metal structure within the barrier lined opening in the dielectric layer, a variety of polishing steps with various slurries are employed.

U.S. Pat. No. 6,217,416 B1 to Kaufman describes a first and second CMP slurry wherein the second slurry includes an abrasive, an oxidizing agent and acetic acid wherein the weight ratio of oxidizing agent/acetic agent is at least 10 and wherein the two slurries are sequentially used in a method to polish a substrate containing copper and containing tantalum or tantalum oxide or both tantalum and tantalum oxide.

U.S. Pat. No. 6,338,744 B1 to Tateyama et al. describe a high purity polishing slurry comprising water and dispersed silica particles.

U.S. Pat. No. 6,261,158 B1 to Holland et al. describes a multi-step CMP system used to polish a wafer to form metal interconnects in a dielectric layer upon which barrier and metal layers have been formed.

U.S. Pat. No. 6,447,371 B2 to Brusic Kaufman et al. describes a chemical mechanical polishing slurry useful for copper/tantalum substrates.

U.S. Pat. No. 6,313,039 B1 to Small et al. describes a chemical mechanical polishing composition and process.

U.S. Pat. No. 6,530,968 B2 to Tsuchiya et al. describes a chemical mechanical polishing slurry.

SUMMARY OF THE INVENTION

Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of polishing metal layers.

Other objects will appear hereinafter.

It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having an upper patterned dielectric layer with an opening therein is provided. A barrier layer is formed over the patterned upper dielectric layer and lining the opening. A metal layer is formed over the barrier layer, filling the opening. A first polish step employing a first slurry composition is conducted to remove a portion of the overlying metal layer. A second polish step employing the first slurry composition is conducted to: polish the partially removed overlying metal layer; and to expose portions of the barrier layer overlying the patterned upper dielectric layer. A third polish step employing a second slurry composition is conducted to remove the exposed barrier layer portions and exposing underlying portions of the patterned upper dielectric layer. A fourth polish step employing the second slurry composition and BTA is conducted to buff the exposed upper dielectric layer portions.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:

FIGS. 1 to 5 schematically illustrate a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Processes Known to the Inventors—Not to be Considered Prior Art

The following metal/copper chemical mechanical polishing processes are known to the inventors and are not to be considered prior art for the purposes of this invention.

For example, when the barrier layer is tantalum nitride (TaN), the dielectric layer is silicon oxide (oxide) and the metal layer is copper (Cu), three polishing options are currently used:

-   -   (1) Cu slurry polish→TaN slurry polish (w/or w/o oxide rate);

-   (2) Cu slurry polish→TaN slurry polish→oxide slurry buff (w/BTA to     selectively not remove Cu); and

-   (3) Cu slurry polish→(clean)→TaN dry etch.

However, options (1) and (2) require consumption of an expensive TaN slurry in order to remove the TaN barrier layer from over the top of the patterned oxide layer; and option (3) requires extra dry etch tools to remove the TaN barrier layer from over the top of the patterned oxide layer. The use of either of these three methods makes it difficult to improve the throughput of the Cu CMP process.

Present Invention—Initial Structure—FIG. 2

FIG. 1 illustrates the initial structure of the present invention. Structure 10 includes patterned dielectric layer 12 formed thereover to a thickness of preferably from about 10,000 to 12,000 Å and more preferably about 11,100 Å.

Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.

Patterned dielectric layer 12 is preferably comprised of silicon oxide, silicon nitride (SiN), FSG or silicon oxynitride (SiON) and is more preferably silicon oxide.

Patterned dielectric layer 12 includes an opening 14 formed therein which may be a dual damascene opening as shown in the figures.

A barrier layer 16 is preferably formed over patterned dielectric 12, lining opening 14. Barrier layer 16 is preferably formed by electrochemical plating (ECP) or physical vapor deposition (PVD) and more preferably by physical vapor deposition (PVD).

Barrier layer 16 has a thickness of preferably from about 250 to 350 Å and more preferably about 300 Å. Barrier layer 16 is preferably comprised of TaN or Ta and is more preferably TaN.

A metal layer 18 is then formed over barrier layer 16, at least filling barrier layer-lined-opening 14. Metal layer 18 is preferably formed by electro-chemical plating (ECP).

Metal layer 18 has a thickness of preferably from about 6000 to 8000 Å and more preferably about 7000Å. Metal layer 18 is preferably comprised of copper (Cu), aluminum (Al) or gold (Au) and is more preferably copper (Cu).

Polishing of Metal Layer 18—FIGS. 2-4

As discovered by the inventors of the present invention, neither a barrier-layer-specific slurry nor a barrier-layer-etch are necessary to remove the barrier layer 16 over the patterned dielectric layer 12. Only two different slurries are needed to polish/remove three different types of films (metal layer 18, barrier layer 16 and patterned dielectric layer 12).

First Step Polish—First Platen—First Slurry Composition—FIG. 2

As shown in FIG. 2, the wafer/structure of FIG. 1 may be placed upon a first platen in a polisling tool and polished with a First Slurry Composition to polish/remove the bulk of metal layer 18 leaving reduced metal layer 18′ having a thickness of preferably from about 2000 to 4000 Å and more preferably about 3000 Å above the barrier-layer-16-lined patterned dielectric layer 12.

The First Slurry Composition is comprised of 600y-73 Slurry wherein:

600y-73 Slurry—Cabot Copper (Cu) Film Polishing Slurry (Manufactured by Cabot Microelectronics. 8A-7. No. 26, Tai-Yuan St., Chu Pei. Hsin Chu Hsien. Taiwan. 203 R.O.C.) Comprised of:

Al₂O₃: preferably from about 0.4 to 0.6 wt. % and more preferably about 0.5 wt. %;

H₂O₂: preferably from about 2.6 to 3.4 wt. % and more preferably from about 2.8 to 3.2 wt. %;

KOH to adjust pH value; and

benzotriazole (1-H benzotriazole or BTA) as a corrosion behavior inhibitor; and having

-   a) pH: preferably from about 2.8 to 4.3 and more preferably about     4.1; and -   b) size of particles: preferably from about 115 to 155 nm, weight     basis and more preferably from about 120 to 150 nm, weight basis.

This first, bulk metal layer 18, polish is a high rate, bulk metal removal using an iScan Endpoint (Applied Material real time Cu In Situ Rate Monitor (ISRM) Endpoint System thickness monitor using eddy current to catch polishing end time) at:

(1) preferably from about 2.0 to 2.4 psi and more preferably about 2.2 psi for preferably from about 36 to 44 seconds and more preferably about 40 seconds (by end-point); and then

(2) preferably from about 1.0 to 1.4 psi and more preferably about 1.2 psi for preferably from about 18 to 22 seconds and more preferably about 20 seconds (by time).

Second Step Polish—Second Platen—First Slurry Composition—FIG. 3

As shown in FIG. 3, the wafer/structure of FIG. 2 may be transferred to a second platen in the polishing tool and then polished with the First Slurry Composition described above to polish the metal layer 18′ surface 19 and to expose the portions 20, 22 of barrier layer 16 overlying the patterned dielectric layer 12.

This second, final metal layer 18″ polish/barrier layer 16 exposure, polish is a low pressure polish using Full Scan Endpoint (Applied Material In Situ Rate Monitor (ISRM) Endpoint System using a laser beam to catch polishing end time) at preferably from about 1.0 to 1.4 psi and more preferably about 1.2 psi for preferably from about 41 to 49 seconds and more preferably about 45 seconds (by end-point).

Third Step Polish—Second Platen—Second Slurry Composition—FIG. 4

As shown in FIG. 4, the wafer/structure of FIG. 3 is then polished with a Second Slurry Composition on the second platen to remove the portions 20, 22 of barrier layer 16 overlying the patterned dielectric layer 12 to expose potions 24, 26 of the underlying patterned dielectric layer 12.

The Second Slurry Composition is comprised of SS6 Slurry wherein:

SS6 Slurry—Cabot Semi-Sperse® Polishing Slurry (also Manufactured by Cabot Microelectronics. 8A-7, No. 26 Tai-Yuan St., Chu Pei, Hsin Chu Hsien. Taiwan, 203R.O.C.) Diluted to 25% for Solids for Polishing Comprised of:

SiO₂: preferably from about 5.8 to 6.2 wt. % and more preferably about 6.0 wt. %; and

KOH to adjust pH value; and having

-   a) pH: preferably from about 9.8 to 11.4 and more preferably from     about 10.0 to 11.2; and -   b) size of particles: preferably from about 125 to 185 nm, weight     basis and more preferably from about 130 to 180 nm, weight basis.

This third polish step is conducted at preferably from about 1.8 to 2.2 psi and more preferably about 2.0 psi for preferably from about 31 to 39 seconds and more preferably about 35 seconds (by time).

Fourth Step Polish—Third Platen—Second Slurry Composition+BTA—FIG. 5

As shown in FIG. 5, the wafer/structure of FIG. 4 may be transferred to a third platen within the polishing tool and polished with the Second Slurry Composition with BTA to buff the exposed portions 24, 26 of the patterned dielectric layer 12 to form buffed exposed portions 24′, 26′ of the buffed patterned dielectric layer 12′.

From about 0.10 to 0.14% and more preferably about 0.12% benzotriazole (1-H benzotriazole or BTA) (corrosion behavior inhibitor) is added to the SS6 Second Slurry Composition described above as to be selective to polished metal layer 18′″ so as to not appreciably remove polished metal layer 18″″.

This fourth polish step is conducted at preferably from about 1.8 to 2.2 psi and more preferably about 2.0 psi for preferably from about 40 to 60 seconds and more preferably about 50 seconds (by time).

Further processing may then proceed. For example, the structure of FIG. 5 may be cleaned and a silicon nitride (Si₃N₄ or nitride) layer may be deposited.

The inventors have found that besides: (1) being less expensive and simpler that the processes known to the inventors since neither a specific barrier-layer-slurry nor an extra barrier-layer-etch-step are required; and (2) the throughput, i.e. the wafers per hour, is improved; the same performance is achieved when polishing copper metal layers 18 in accordance with their present invention including defects, resistance (Rs) value and stress migration (SM) test. One of the most serious problems in Cu-based multilevel integration is the failures in stacked via resistance caused by stress-induced voids in via holes. So passing the SM test by the structure(s) formed in accordance with the method of the present invention is the index for Cu-based process.

A better slope of pattern density correlating with the Rs value is also achieved as compared to the current processes known to the inventors. Further, when polishing copper metal layers 18 in accordance with their present invention, the inventors have found that dishing, erosion and tiger teeth were appreciably reduced.

Advantages of the Present Invention

The advantages of one or more embodiments of the present invention include:

-   1. simpler method; -   2. less expensive method; -   3. improved dishing, erosion and tiger teeth; -   4. increased wafers/hour is achieved; -   5. SM test passed; and -   6. Rs value acceptable.

While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims. 

1. A method for polishing a semiconductor structure, comprising: providing a semiconductor structure having first, second and third material layers; conducting a first polishing step to remove a first portion of the first material layer; conducting a second polishing step to remove a second portion of the first material layer and to expose a surface of the second material layer; conducting a third polishing step to remove at least a portion of the second material layer and to expose a surface of the third material layer; conducting a fourth polishing step to buff the exposed surface of the third material layer; wherein the first polishing step comprises using a first slurry, and the third polishing step comprises using a second slurry, and wherein the first and second slurries have different compositions.
 2. The method of claim 1, wherein the second polishing step comprises using the first slurry and the fourth polishing step comprises using the second slurry.
 3. The method of claim 1, wherein the first slurry has a pH of from about 2.8 to about 4.3 and a particle size of from about 115 nm to about 155 nm; and the second slurry has a pH of from about 9.8 to about 11.4 and a particle size of from about 125 to about 185 nm.
 4. The method of claim 1, wherein the second slurry comprises a corrosion inhibitor.
 5. The method of claim 1, wherein the first material layer comprises a dielectric material, the second layer comprises a barrier material and the third material layer comprises a conductive material.
 6. The method of claim 4, wherein the conductive material comprises copper, aluminum or gold.
 7. The method of claim 4, wherein the barrier material comprises Tantalum or Tantalum Nitride.
 8. A method for polishing a multi-layered structure, comprising: providing a semiconductor structure having a plurality of material layers; conducting a first polishing step using a first slurry to remove a first portion of the plurality of material layers; conducting a second polishing step using the first slurry to remove a second portion of the plurality of material layers; conducting a third polishing step using a second slurry to remove a third portion of the plurality of material layers; conducting a fourth polishing step using the second slurry to remove a fourth portion of the plurality of material layers; wherein the first and second slurries have substantially different compositions.
 9. The method of claim 8, wherein the first slurry is acidic.
 10. The method of claim 9, wherein the first slurry has a pH of from about 2.8 to about 4.3.
 11. The method of claim 8, wherein the second slurry is alkaline.
 12. The method of claim 11, wherein the second slurry has a pH of from about 9.8 to about 11.4.
 13. The method of claim 8, wherein the first slurry comprises particles having a size of from about 115 nm to about 155 nm; and the second slurry comprises particles having a size of from about 125 to about 185 nm.
 14. The method of claim 8, wherein the first polishing step is performed at a first polishing pressure for a first time period and a second polishing pressure for a second time period, wherein the first polishing pressure is greater than the second polishing pressure.
 15. The method of claim 14, wherein the first polishing pressure is from about 2.0 to about 2.4 psi, and the second polishing pressure is from about 1.0 psi to about 1.4 psi.
 16. The method of claim 8, wherein the second slurry further comprises a corrosion inhibitor.
 17. A method for performing chemical-mechanical polishing (CMP), comprising: providing a semiconductor structure having a dielectric layer, a barrier layer overlying at least a portion of the dielectric layer, and a metal layer overlying at least a portion of the barrier layer; conducting a first CMP step using an acidic slurry to remove a first thickness of the semiconductor structure; conducting a second CMP step the acidic slurry to remove a second thickness of the semiconductor structure; conducting a third CMP step using an alkaline slurry to remove a third thickness of the semiconductor structure; conducting a fourth CMP step using the alkaline slurry to remove a fourth thickness of the semiconductor structure; wherein the first CMP step comprises removing at least a portion of the metal layer and the fourth CMP step comprises buffing a surface of the dielectric layer.
 18. The method of claim 17, wherein the acidic slurry has a pH of from about 2.8 to about 4.3.
 19. The method of claim 17, wherein the alkaline slurry has a pH of from about 9.8 to about 11.4.
 20. The method of claim 17, wherein the first slurry comprises particles having a size of from about 115 nm to about 155 nm; and the second slurry comprises particles having a size of from about 125 to about 185 nm.
 21. The method of claim 17, wherein the first CMP step is carried out at a first polishing pressure for a first time period and a second polishing pressure for a second time period, wherein the first polishing pressure is greater than the second polishing pressure.
 22. The method of claim 17, wherein the first polishing pressure is from about 2.0 psi to about 2.4 psi, and the second polishing pressure is from about 1.0 to about 1.4 psi.
 23. The method of claim 17, wherein the alkaline slurry further comprises a corrosion inhibitor. 